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W3DG7232V-D2
PRELIMINARY*
256MB - 32Mx72 SDRAM, REGISTER and SPD, w/PLL
FEATURES
Burst Mode Operation Auto and Self Refresh capability LVTTL compatible inputs and outputs Serial Presence Detect with EEPROM Fully synchronous: All signals are registered on the positive edge of the system clock Programmable Burst Lengths: 1, 2, 4, 8 or Full Page 3.3V 0.3V Power Supply 168 Pin DIMM JEDEC
NOTE: Consult factory for availability of: * Lead-Free Products * Vendor source control options * Industrial temperature options * This product is under development, is not qualified or characterized and is subject to change without notice.
DESCRIPTION
The W3DG7232V is a 32Mx72 synchronous DRAM module which consists of nine 32Meg x 8 SDRAM components in TSOP II package, two 18 bit Drive ICs for input control signal and one 2Kb EEPROM in an 8 pin TSSOP package for Serial Presence Detect which are mounted on a 168 pin DIMM multilayer FR4 Substrate.
PIN CONFIGURATIONS (FRONT SIDE/BACK SIDE)
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 FRONT VSS DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VCC DQ14 DQ15 CB0 CB1 VSS NC NC VCC WE# DQMB0 PIN 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 BACK DQMB1 CS0# DNU VSS A0 A2 A4 A6 A8 A10/AP BA1 VCC VCC CK0 VSS DNU CS2# DQMB2 DQMB3 DNU VCC NC NC CB2 CB3 VSS DQ16 DQ17 PIN 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 FRONT DQ18 DQ19 VCC DQ20 NC *VREF *CKE1 VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 VCC DQ28 DQ29 DQ30 DQ31 VSS *CK2 NC NC **SDA **SCL VCC PIN 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 BACK VSS DQ32 DQ33 DQ34 DQ35 VCC DQ36 DQ37 DQ38 DQ39 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 VCC DQ46 DQ47 CB4 CB5 VSS NC NC VCC CAS# DQMB4 PIN 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 BACK DQMB5 *CS1# RAS# VSS A1 A3 A5 A7 A9 BA0 A11 VCC *CK1 A12 VSS CKE0 *CS3# DQMB6 DQMB7 *A13 VCC NC NC CB6 CB7 VSS DQ48 DQ49
1
PIN NAMES
BACK DQ50 DQ51 VCC DQ52 NC *VREF REGE VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 VCC DQ60 DQ61 DQ62 DQ63 VSS *CK3 NC **SA0 **SA1 **SA2 VCC
PIN 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168
A0 - A12 BA0-1 DQ0-63 CB0-7 CK0 CKE0 CS0#, CS2# RAS# CAS# WE# DQMB0-7 VCC VSS *VREF REGE SDA SCL SA0-2 DNU NC
Address Input (Multiplexed) Select Bank Data Input/Output Check Bit (Data-In/Data-Out) Clock Input Clock Enable Input Chip Select Input Row Address Strobe Column Address Strobe Write Enable DQMB Power Supply (3.3V) Ground Power Supply for Reference Register Enable Serial Data I/O Serial Clock Address in EEPROM Do Not Use No Connect
* These pins are not used in this module. ** These pins should be NC in the system which does not support SPD.
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FUNCTIONAL BLOCK DIAGRAM
W3DG7232V-D2
PRELIMINARY
CS0# DQMB0
DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS
DQMB4
DQM DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS
DQMB1
DQM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS
DQMB5
DQM DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS
CK0
SDRAM PLL REGISTER
12pF
DQMB6
DQM CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS
CK1-CK3
12pF
SERIAL PD SCL A0 A1 SA1 A2 SA2 SDA
CS2# DQMB2
DQM DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS
DQMB7
DQM DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS
SA0
VCC VSS
SDRAM SDRAM
DQMB3
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS
NOTE: DQ wiring may differ than described in this drawing, however DQ/DQMB/CKE/S relationships must be maintained as shown.
CS0#/CS2# DQMB0 - DQMB7 BA0 - BA1 A0 - A12 RAS# CAS# CKE0 WE# REGE PCK
R E G I S T E R
RCS0#/RCS2# RDQMB0 - RDQMB7 RBA0 - RBA1: SDRAMS RA0 - RA12: SDRAMS RRAS#: SDRAMS RCAS#: SDRAMS RCKE0: SDRAMS RWE#: SDRAMS
* Wire per Clock Loading Table/Wiring Diagrams
NOTE: All resistor values are 10 ohms.
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ABSOLUTE MAXIMUM RATINGS
Parameter Voltage on any pin relative to VSS Voltage on VCC supply relative to VSS Storage Temperature Power Dissipation Short Circuit Current Symbol VIN, VOUT VCC, VCCQ TSTG PD IOS Value -1.0 ~ 4.6 -1.0 ~ 4.6 -55 ~ +150 9 50
W3DG7232V-D2
PRELIMINARY
Units V V C W mA
Note: Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
Voltage Referenced to: VSS = 0V, 0C TA 70
Parameter Supply Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Input Leakage Current Symbol VCC VIH VIL VOH VOL ILI Min 3.0 2.0 -0.3 2.4 -- -10 Typ 3.3 3.0 -- -- -- -- Max 3.6 VCCQ+0.3 0.8 -- 0.4 10 Unit V V V V V A 1 2 IOH= -2mA IOL= -2mA 3 Note
Note: 1. VIH (max)= 5.6V AC. The overshoot voltage duration is 3ns. 2. VIL (min)= -2.0V AC. The undershoot voltage duration is 3ns. 3. Any input 0V VIN VCCQ Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE
TA = 25 C, f = 1MHz, VCC = 3.3V, VREF = 1.4V 200mV
Parameter Input Capacitance (A0-A12) Input Capacitance (RAS#,CAS#,WE#) Input Capacitance (CKE0) Input Capacitance (CLK0) Input Capacitance (CS0#,CS2#) Input Capacitance (DQMB0-DQMB7) Input Capacitance (BA0-BA1) Data input/output capacitance (DQ0-DQ63) Data input/output capacitance (CB0-CB7) Symbol CIN1 CIN2 CIN3 CIN4 CIN5 CIN6 CIN7 COUT COUT1 Max 50 50 50 6 50 13 50 16 16 Unit pF pF pF pF pF pF pF pF pF
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OPERATING CURRENT CHARACTERISTICS
VCC = 3.3V, 0C TA 70C
Parameters Symbol Conditions
W3DG7232V-D2
PRELIMINARY
Versions 133/100
Units mA
Note 1
Operating Current (One bank active) Precharge Standby Current in Power Down Mode Active standby in current non powerdown mode Operating current (Burst mode)
ICC1
Burst Length = 1 tRC tRC(min) IOL = 0mA CKE VIL(max), tCC = 10ns CKE VIH(min), CS VIH(min), tCC = 10ns Input signals are charged one time during 20ns Io = mA Page burst 4 Banks activated tCCD = 2CLK tRC tRC(min) CKE 0.2V
900
ICC2P ICC3N
18 270
mA mA
3 3
ICC4
990
mA
1
Refresh current Self refresh current
Notes: 1. Measured with outputs open. 2. Refresh period is 64ms. 3. Measured with 1 PLL & 2 Drive ICs.
ICC5 ICC6
1980 27
mA mA
2 3
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VCC, VCCQ = +3.3V 0.3V AC CHARACTERISTICS PARAMETER Access timefrom CLK (pos.edge) CL = 3 CL = 2 Address hold time Address setup time CLK high-level width CLK low-level width Clock cycle time CL = 3 CL = 2 CKE hold time CKE setup time CS#, RAS#, CAS#, WE#, DQM hold time CS#, RAS#, CAS#, WE#, DQM setup time Data-in hold time Data-in setup time Data-out high-impedance time CL = 3 CL = 2 Data-out low-impedance time Data-out hold time (load) Data-out hold time (no load) ACTIVE to PRECHARGE command ACTIVE to ACTIVE command period ACTIVE to READ or WRITE delay Refresh period AUTOREFRESH period PRECHARGE command period ACTIVE bank a to ACTIVE bank b command Transition time WRITE recovery time SYMBOL tAC(3) tAC(2) tAH tAS tCH tCL tCK(3) tCK(2) tCKH tCKS tCMH tCMS tDH tDS tHZ(3) tHZ(2) tLZ tOH tOHN tRAS tRC tRCD tREF tRFC tRP tRRD tT tWR 66 15 14 0.3 1 CLK + 7ns 14 Exit SELF REFRESH to ACTIVE command tXSR 67 1.2 1 2.7 1.8 37 60 15 64 66 20 15 0.3 1 CLK + 7.5ns 15 75 1.2 120,000 0.8 1.5 2.5 2.5 7 7.5 0.8 1.5 0.8 1.5 0.8 1.5 5.4 5.4 1 2.7 1.8 44 66 20 64 66 20 15 0.3 1 CLK + 7.5ns 15 80 120,000 MIN 7 MAX 5.4 5.4 0.8 1.5 2.5 2.5 7.5 10 0.8 1.5 0.8 1.5 0.8 1.5 5.4 6 1 2.7 1.8 50 66 20 MIN 7.5 MAX 5.4 6 1 2 3 3 8 10 1 2 1 2 1 2 MIN
W3DG7232V-D2
PRELIMINARY
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
10 MAX 6 6 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns 6 6 ns ns ns ns ns 120,000 ns ns ns 64 ms ns ns ns 1.2 ns 7 24 28 10 10 23 23 NOTE 27
ns ns
25 20
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AC FUNCTIONAL CHARACTERISTICS
VCC, VCCQ = +3.3V 0.3V PARAMETER READ/WRITE command to READ/WRITE command CKE to clock disable or power-down entry mode CKE to clock enable or power-down exit setup mode DQM to input data delay DQM to data mask during WRITEs DQMto data high-impedance during READs WRITE command to input data delay Data-into ACTIVE command Data-into PRECHARGE command Last data-in to burst STOP command Last data-in to new READ/WRITE command Lastdata-into PRECHARGE command LOADMODEREGISTER command to ACTIVE or REFRESH command Data-out to high-impedance from PRECHARGE command CL = 3 CL = 2 SYMBOL tCCD tCKED tPED tDQD tDQM tDQZ tDWD tDAL tDPL tBDL tCDL tRDL tMRD tROH(3) tROH(2) 7 1 1 1 0 0 2 0 4 2 1 1 2 2 3 2 7.5 1 1 1 0 0 2 0 5 2 1 1 2 2 3 2
W3DG7232V-D2
PRELIMINARY
10 1 1 1 0 0 2 0 5 2 1 1 2 2 3 2
UNITS tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK
NOTES 17 14 14 17 17 17 17 15, 21 16, 21 17 17 16, 21 26 17 17
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Notes 1. All voltages referenced to VSS. 2. This parameter is sampled. VCC, VCCQ = +3.3V; TA = 25C; pin under test biased at 1.4V; f = 1 MHz. 3. IDD is dependent on output loading and cycle rates. Specified values are obtained with mini-mum cycle time and the outputs open. 4. Enables on-chip refresh and address counters. 5. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range is ensured. 6. An initial pause of 100s is required after power-up, followed by two AUTO REFRESH commands, before proper device operation is ensured. (VCC and VCCQ must be powered up simultaneously. VSS and VSSQ must be at same potential.) The two AUTO REFRESH command wake-ups should be repeated any time the tREF refresh requirement is exceeded. 7. AC characteristics assume tT = 1ns. 8. In addition to meeting the transition rate specification, the clock and CKE must transit between VIH and VIL (or between VIL and VIH) in a mono-tonic manner. 9. Outputs measured at 1.5V with equivalent load: Q 50pF
W3DG7232V-D2
PRELIMINARY
10. tHZ defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL. The last valid data element will meet tOH before going High-Z. 11. AC timing and IDD tests have VIL = 0V and VIH = 3V with timing referenced to 1.5V crossover point. If the input transition time is longer than 1ns, then the timing is referenced at VIL (MAX) and VIH (MIN) and no longer at the 1.5V crossover point. 12. Other input signals are allowed to transition no more than once every two clocks and are other-wise at valid VIH or VIL levels. 13. IDD specifications are tested after the device is properly initialized. 14. Timing actually specified by tCKS; clock(s) specified as a reference only at minimum cycle rate. 15. Timing actually specified by tWR plus tRP; clock(s) specified as a reference only at minimum cycle rate.
16. Timing actually specified by tWR. 17. Required clocks are specified by JEDEC functionality and are not dependent on any timing parameter. 18. The IDD current will increase or decrease proportionally according to the amount of frequency alteration for the test condition. 19. Address transitions average one transition every two clocks. 20. CLK must be toggled a minimum of two times during this period. 21. Based on tCK = 10ns for 10, and tCK = 7.5ns for 7 and 7.5. 22. VIH overshoot: VIH (MAX) = VCCQ + 2V for a pulse width 3ns, and the pulse width cannot be greater than one third of the cycle rate. VIL under-shoot: VIL (MIN) = -2V for a pulse width 3ns. 23. The clock frequency must remain constant (stable clock is defined as a signal cycling within timing constraints specified for the clock pin) during access or precharge states (READ, WRITE, including tWR, and PRECHARGE commands). CKE may be used to reduce the data rate. 24. Auto precharge mode only. The precharge timing budget (tRP) begins 7ns for 7; 7.5ns for 7.5 and 7.5ns for 10 after the first clock delay, after the last WRITE is executed. May not exceed limit set for precharge mode. 25. Precharge mode only. 26. JEDEC and PC133, PC100 specify three clocks. 27. tAC for 7/7.5 at CL = 3 with no load is 4.6ns and is guaranteed by design. 28. Parameter guaranteed by design.
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ORDERING INFORMATION FOR D2
Part Number W3DG7232V10D2 W3DG7232V7D2 W3DG7232V75D2 Speed 100MHz 133MHz 133MHz CAS Latency CL=2 CL=2 CL=3 Height*
W3DG7232V-D2
PRELIMINARY
30.48 (1.20") 30.48 (1.20") 30.48 (1.20")
NOTES: * Consult Factory for availability of Lead-Free products. (F = Lead-Free, G = RoHS Compliant) * Vendor specific part numbers are used to provide memory components source control. The place holder for this is shown as lower case "x" in the part numbers above and is to be replaced with the respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others) * Consult factory for availability of industrial temperature (-40C to 85C) option
PACKAGE DIMENSIONS
3.99 (0.157) (2X)
3.18 (0.125) (2X)
133.48 (5.255) MAX. SEE NOTE 1
4.32 (0.170) MAX.
30.48 (1.20) 17.78 MAX. (0.700) 11.43 (0.450)
36.83 (1.450) 6.35 (0.250) 42.19 (1.661) 115.57 (4.550) 6.35 (0.250)
54.61 (2.150)
3.99 (0.157) MIN. 1.27 0.10 (0.050 0.004)
MEASURED AFTER PLATING OVER FINGERS.
15.60 (0.614)
ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)
February 2005 Rev. 1
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Document Title
256MB - 32Mx72 SDRAM, REGISTER and SPD, w/ PLL
W3DG7232V-D2
PRELIMINARY
Revision History Rev #
Rev A Rev B
History
History page B.1 Changed block diagram B.2 Changed module height to 1.10 B.3 Add order information
Release Date
10-25-01 1-15-02
Status
Advanced Advanced
Rev 0
0.1 Updated CAP and IDD Specs 0.2 Removed "ED" from part number 0.3 Added new title page 0.4 Moved from Advanced to Preliminary
7-2004
Preliminary
Rev 1
1.1 Added AC specs
2-2005
Preliminary
February 2005 Rev. 1
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